![]() ![]() ![]() In write-through protocol when a processor modifies a data block in its cache, it immediately updates the main memory with the new copy of the same data block. If it wants to read or write/modify this data block it has to send a request to the owner of the same data block. Invalid (I): The cache has a data block that does not have valid data.Shared (S): A data block in the main memory is shared by many processors in the system and all the processors have a valid copy of the data block in their caches.Here, the processor is the exclusive owner of the data block. So, the data block to be modified is now only with the processor that wishes to modify it and with the main memory. ![]() Exclusive (E): When the processor wants to modify a data block in its cache, it broadcast the request to invalidate the copy of the same data block in other caches.If the processor wants to modify it again, it doesn’t need to broadcast this request over the bus again. The main memory copy for the same data block does not contain the modified value of the data block. This copy of the data block is not available with any other caches in the system. Modify (M): The data block in a cache is modified and the processor modifying the data block is the owner of that data block.So the cache controller maintains the state for every cache block of the cache memory which helps in maintaining the coherency. Now to maintain the cache coherency the cache controller maintain some information to keep the the caches of other processors in the system synchronized, while a processor is modifying its copy of data that is also shared by other processors in the system. If it is not there the data is retrieved from the main memory and a copy of it is placed in the cache block. And whenever a processor requires a data block it first checks it in its own cache memory. If we talk about the cache memory it is subdivided into a number of blocks. But before getting into the protocols we will discuss some terminologies associated to cache coherence problem. Well, this cache coherence problem can be sorted using the protocols discussed below. The figure below shows the cache coherence problem in a multiprocessing environment. And this problem is the cache coherence problem. But, the main memory and other processors’ cache will have the old copy of the shared memory block X. As the processor P1 will have the modified copy of the shared memory block i.e. In case, the processor P1 modifies the copy of shared memory block X present in its cache. The figure below shows how processors P1, P3 & Pn have the copy of shared data block X of main memory in their caches. Processors may share the same data block by keeping a copy of this data block in their cache. Now, keeping a common cache for all the processors will enhance the size of the cache thereby slowing down the performance of the system.įor better performance, each processor implements its own cache. In a multiprocessor environment, all the processors in the system share the main memory via a bus. Content: Cache Coherence in Computer Architecture In this section, we will discuss the cache coherence problem and the protocol for resolving the cache coherence problem. ![]()
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